Year 3 Sem 1

They said (CEG yearly briefing) that Year 2 might be the hardest year for CEG students. Reasons include a shift from scientific fundamentals towards year 2 breadth modules, of which half you might not like. Instead, I beg to differ. Year 3 Sem 1 would be the paradigm shift instead. This is because we move away from pure content towards more independent projects. You would have experienced projects in Year 1 and Year 2, but this is different. Year 1 and 2 projects have a few ‘milestone’ submissions or are divided into different parts in order to help guide you along. Year 3 onwards, modules might be pure project and design. At the same time, module content would be more technical and in-depth. You might have disliked EE2023 Signals and Systems for the heavy use of mathematics, but project and design modules are harder since you have an almost blank slate. You actually have to think really hard and remember all your fundamentals! Although there are some milestones, you are literally on your own. One distinct difference in level 3000 modules is the lack of ‘tutorials’ i.e. there are no formal tutorial sessions and hence tutorials are conducted lecture style. I will describe the modules in this semester.

CG3002 – Embedded Systems Design Project (100% design project, no exam and a whopping 6MCs) (Dr Colin Tan, Uncle Soo, Prof Tay Teng Tiow)

This is the CEG capstone project in which you have to apply everything that you have learnt from all the modules you have taken so far, namely: CG1101, CG1103, CG1108, CS2103, CG2271, EE2021, EE2020 and CG2007. Remember CICMS from CG1103? In this capstone project, you are returned to the hypothetical CEG Hypermarket system and have to develop a hardware cashier system that can interface with a PC and on-line database servers. For the cashier machine, you will have to knock off 3 months of slumber when you see a familiar PCB and 80188 uP from CG2007. This time, you also have to apply all the EE2020 digital fundamentals and EE2021/EE2031 circuits theory to design a circuit that is controlled by the 80188 with peripherals like six 7-segment displays controlled by only 2 latches, a digital to analogue converter (DAC) hooked up to a power amplifier and a speaker that can play sound, a megabit UV erasable EPROM that can store up to 256KB of data and two numeric digit keypads. All conveniently wire-wrapped by you! The 80188 is also hooked up to a UART peripheral which can communicate with a PC through RS232 serial. the 80188 has to also be conveniently programmed in assembly. You apply the RTOS theory you learnt in CG2271 and program your RTOS for the cashier in x86 assembly. You then apply the CS2103 and CG1103 theory to design the PC software to communicate with the cashier through the aforementioned RS232 serial. While you are at it, you will also have to design a database to store the ‘CEG hypermarket’ information. A slight advantage if you took CS2102 (Database Systems). I will tell you why it is hard. You start off with only one deadline in sight: the marking deadline at the end of week 15 (after exams). You can slack off most of the time and end up still debugging hardware in week 9 like now. Along the way, the lecturers will give lectures to “guide” you along, but there is no strict answer or methodology. My advice, have your 6 man team consist of a balanced pool of talent. Make sure you have 2 specialists in hardware, 2 assembly specialists and 2 software engineering specialists. This is because you will be graded by the three components and therefore three lecturers: Dr Tay for hardware, Dr Colin for the RTOS and Dr Soo for the software engineering aspect. Also, if your hardware fails on presentation day (which is very possible), you WILL fail the hardware component.

“Any small mistake you make in your circuit, you can easily pay back in weeks of debugging” ~Dr Tay.

CG3207 – Computer Architecture (I was taught by Dr Tay Teng Tiow)

In this module you will be the microprocessor designer and learn how a microprocessor is put together. You learn about how the microprocessor is designed based on the proven theory that all mathematical operations can be done with only add, subtract, logic gates, memory move and conditional instructions. (Instruction set completeness). In the project, it is your job to completely design the Intel 8051 uP in VHDL and verify it’s operation on FPGA. You will have to fill in a bare skeleton template with several thousand lines of VHDL code. The exams test not so much on memory or content but about what he described in lectures. It requires that you produce the 8051 to specifications found on the data-sheet which only tells you the required outcome, not how to implement it. One advice: the 8051 architecture is much different from the hypothetical uP-3207 he describes in lectures although the underlying conceptual theory is the same. No mid-term but there are fortnightly IVLE quizzes, that 8051 project and a final exam.

“The mysterious uP black-box isn’t so mysterious after all.”

EE3204 – Computer Communication Networks I

(I was taught by Dr Mohan Gurusamy and Dr Mehul Motani) In this module you learn about how the networks that connect you to the Internet right now work. Networking concepts are taught together with one lab work submission, 2 quizzes and a final exam. This module is a little more theoretical than the previous two.

EG2401 – Engineering Professionalism

This 3 MC module is taught jointly by four lecturers taking 6 hours each. It focuses on responsible and ethical behaviour required of engineers. You will also learn the reason for having to take the module itself, along with all the required GEMs, breadths, fundamental theory, design and projects and even FYP. (For global accreditation of your degree). No mid-term but there is a term-paper done in a group regarding an ethical case study. There is a final exam.

EE4214 – Real Time Embedded Systems (I was taught by Dr Akash Kumar)

This is a embedded systems technical elective. It is literally CG2271 over again plus more. Originally everyone is supposed to apply the real-time concepts to a ‘soccer’ project but previous years have complained about the difficulty and hence now the project is optional. If you don’t want to do the project, your CA is graded on a series of lab work. You have to use the Spartan 3E-1600 Starter board and implement real-time concepts based on the lab questions on a dual-core Xilinx Microblaze IP programmed to the FPGA. If CG2271 was hard, this is harder. Although the microblaze is programmed in C, the API documentation for microblaze and the propriety Xilkernel RTOS is rather poor. I find the documentation API writing in English but whose sentences are incomprehensible and therefore spend hours hacking at the functions. Overall, it is a good module for embedded systems. Exam is difficult as expected (Prof Akash’s exams are not easy).

This entry was posted in CEG, Modules and tagged , , , , , , , , . Bookmark the permalink.

One Response to Year 3 Sem 1

Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Google+ photo

You are commenting using your Google+ account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )


Connecting to %s